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发表于 2025-3-18 17:55:36
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- module VIP_multi_target_detect
- (
- input clk,
- input rst_n,
- input per_frame_vsync,
- input per_frame_hs,
- input per_frame_clken,
- input per_img_Bit, //white
- output reg [42:0] target_pos_out1, // {Flag,ymax[41:32],xmax[31:21],ymin[20:11],xmin[10:0]}
- output reg [42:0] target_pos_out2,
-
- input [ 9:0] MIN_DIST //min domain
- );
-
- //720p
- parameter [10:0] IMG_HDISP = 11'd1280;
- parameter [9:0] IMG_VDISP = 10'd720 ;
-
- //lag 1 clocks signal sync
- reg per_frame_vsync_r;
- reg per_frame_hs_r ;
- reg per_frame_clken_r;
- reg per_img_Bit_r ;
-
- always@(posedge clk or negedge rst_n)begin
- if(!rst_n)begin
- per_frame_vsync_r <= 0;
- per_frame_hs_r <= 0;
- per_frame_clken_r <= 0;
- per_img_Bit_r <= 0;
- end
- else begin
- per_frame_vsync_r <= per_frame_vsync ;
- per_frame_hs_r <= per_frame_hs ;
- per_frame_clken_r <= per_frame_clken ;
- per_img_Bit_r <= per_img_Bit ;
- end
- end
-
- wire vsync_pos_flag;//rising edge of vs
- wire vsync_neg_flag;//falling edge if vs
-
- assign vsync_pos_flag = per_frame_vsync & (!per_frame_vsync_r);
- assign vsync_neg_flag = !(per_frame_vsync) & per_frame_vsync_r;
-
- //
- //count the input pixel of v/h to get v/h coordinates
-
- reg [10:0] x_cnt;
- reg [9:0] y_cnt;
-
- always@(posedge clk or negedge rst_n) begin
- if(!rst_n) begin
- x_cnt <= 11'd0;
- y_cnt <= 10'd0;
- end
- else if(!per_frame_vsync) begin
- x_cnt <= 11'd0;
- y_cnt <= 10'd0;
- end
- else if(per_frame_clken) begin
- if(x_cnt < IMG_HDISP - 1) begin
- x_cnt <= x_cnt + 1'b1;
- y_cnt <= y_cnt;
- end
- else begin
- x_cnt <= 11'd0;
- y_cnt <= y_cnt + 1'b1;
- end
- end
- else begin
- x_cnt <= 11'd0;
- y_cnt <= y_cnt;
- end
- end
-
-
- // lag 1 clocks signal sync
- reg [10:0] x_cnt_r;
- reg [9:0] y_cnt_r;
-
- always @(posedge clk or negedge rst_n) begin
- if (!rst_n)
- x_cnt_r <= 11'd0;
- else
- x_cnt_r <= x_cnt;
- end
-
- always @(posedge clk or negedge rst_n) begin
- if (!rst_n)
- y_cnt_r <= 10'd0;
- else
- y_cnt_r <= y_cnt;
- end
-
- // reg the boundaries of each moving object
- reg [42:0] target_pos1;
- reg [42:0] target_pos2;
-
- // valid mark
- wire [1:0]target_flag;
-
- // left/right/up/down fields for each target
- wire [10:0] target_left1 ;
- wire [10:0] target_right1 ;
- wire [9:0] target_top1 ;
- wire [9:0] target_bottom1 ;
-
- wire [10:0] target_left2 ;
- wire [10:0] target_right2 ;
- wire [9:0] target_top2 ;
- wire [9:0] target_bottom2 ;
-
-
- assign target_flag[0] = target_pos1[42];
-
- assign target_bottom1 = (target_pos1[41:32] < IMG_VDISP-1 - MIN_DIST ) ? (target_pos1[41:32] +MIN_DIST) : IMG_VDISP-1;
- assign target_right1 = (target_pos1[31:21] < IMG_HDISP-1 - MIN_DIST ) ? (target_pos1[31:21] +MIN_DIST) : IMG_HDISP-1;
- assign target_top1 = (target_pos1[20:11] > 10'd0 + MIN_DIST ) ? (target_pos1[20:11] -MIN_DIST) : 10'd0;
- assign target_left1 = (target_pos1[10: 0] > 11'd0 + MIN_DIST ) ? (target_pos1[10: 0] -MIN_DIST) : 11'd0;
-
- assign target_flag[1] = target_pos2[42];
-
- assign target_bottom2 = (target_pos2[41:32] < IMG_VDISP-1 - MIN_DIST ) ? (target_pos2[41:32] +MIN_DIST) : IMG_VDISP-1;
- assign target_right2 = (target_pos2[31:21] < IMG_HDISP-1 - MIN_DIST ) ? (target_pos2[31:21] +MIN_DIST) : IMG_HDISP-1;
- assign target_top2 = (target_pos2[20:11] > 10'd0 + MIN_DIST ) ? (target_pos2[20:11] -MIN_DIST) : 10'd0;
- assign target_left2 = (target_pos2[10: 0] > 11'd0 + MIN_DIST ) ? (target_pos2[10: 0] -MIN_DIST) : 11'd0;
-
-
- reg target_cnt;
- reg [1:0] new_target_flag; //ballot box
-
- always @(posedge clk or negedge rst_n) begin
- if (!rst_n) begin
- target_pos1 <= {1'b0, 10'd0, 11'd0, 10'd0, 11'd0};
- target_pos2 <= {1'b0, 10'd0, 11'd0, 10'd0, 11'd0};
- new_target_flag <= 2'd0;
- target_cnt <= 1'd0;
- end
-
- // initialize
- else if(vsync_pos_flag) begin
- target_pos1 <= {1'b0, 10'd0, 11'd0, 10'd0, 11'd0};
- target_pos2 <= {1'b0, 10'd0, 11'd0, 10'd0, 11'd0};
- new_target_flag <= 2'd0;
- target_cnt <= 1'd0;
- end
- else begin
- // first clk,judge new target/target in domain
- if(per_frame_clken && per_img_Bit ) begin
- if(target_flag[0] == 1'b0) // if reg flag0 invalid,vote the bit as a new target
- new_target_flag[0] <= 1'b1;
- else begin // if reg flag0 valid,judge whether the target is in domain
- if((x_cnt < target_left1 || x_cnt > target_right1 || y_cnt < target_top1 || y_cnt > target_bottom1)) //if out of domain,vote the bit as a new target
- new_target_flag[0] <= 1'b1;
- else
- new_target_flag[0] <= 1'b0;
- end
-
- if(target_flag[1] == 1'b0) // same as flag0
- new_target_flag[1] <= 1'b1;
- else begin
- if((x_cnt < target_left2 || x_cnt > target_right2 || y_cnt < target_top2 || y_cnt > target_bottom2))
- new_target_flag[1] <= 1'b1;
- else
- new_target_flag[1] <= 1'b0;
- end
- end
- else begin
- new_target_flag <= 2'b0;
- end
-
-
- // second clk,according to the vote,update target
- if(per_frame_clken_r && per_img_Bit_r) begin
- if(new_target_flag == 2'b11) begin // unanimous vote,new target appear
- if(target_cnt == 1'b0)begin
- target_cnt <=1'd1;
- target_pos1 <= {1'b1, y_cnt_r, x_cnt_r, y_cnt_r, x_cnt_r};
- end
- else if(target_cnt == 1'b1 && target_pos2[42] != 1'b1 && (x_cnt_r < target_left1 || x_cnt_r > target_right1 || y_cnt_r < target_top1 || y_cnt_r > target_bottom1))begin
- target_pos2 <= {1'b1, y_cnt_r, x_cnt_r, y_cnt_r, x_cnt_r};
- target_cnt <=1'd1;
- end
- end
-
- else if (new_target_flag > 2'd0 && new_target_flag != 2'b11) begin // target in domain
- if(new_target_flag[0] == 1'b0) begin // flag0 == 0, target in domain1
-
- target_pos1[42] <= 1'b1;
-
- if(x_cnt_r < target_pos1[10: 0]) // expand boundary
- target_pos1[10: 0] <= x_cnt_r;
- if(x_cnt_r > target_pos1[31:21])
- target_pos1[31:21] <= x_cnt_r;
- if(y_cnt_r < target_pos1[20:11])
- target_pos1[20:11] <= y_cnt_r;
- if(y_cnt_r > target_pos1[41:32])
- target_pos1[41:32] <= y_cnt_r;
- end
- else if(new_target_flag[1] == 1'b0) begin // flag1 == 0, target in domain2
-
- target_pos2[42] <= 1'b1;
-
- if(x_cnt_r < target_pos2[10: 0])
- target_pos2[10: 0] <= x_cnt_r;
- if(x_cnt_r > target_pos2[31:21])
- target_pos2[31:21] <= x_cnt_r;
- if(y_cnt_r < target_pos2[20:11])
- target_pos2[20:11] <= y_cnt_r;
- if(y_cnt_r > target_pos2[41:32])
- target_pos2[41:32] <= y_cnt_r;
- end
- end
- end
- end
- end
-
- //reg output after a frame
-
- always @(posedge clk or negedge rst_n)
- if(!rst_n) begin
- target_pos_out1 <= {1'd0,10'd0,11'd0,10'd0,11'd0};
- target_pos_out2 <= {1'd0,10'd0,11'd0,10'd0,11'd0};
- end
- else if(vsync_neg_flag) begin
- target_pos_out1 <= target_pos1;
- target_pos_out2 <= target_pos2;
- end
-
-
- endmodule
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